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CY7C1049DV33
4-Mbit (512K x 8) Static RAM
Features
* Pin- and function-compatible with CY7C1049CV33 * High speed -- tAA = 10 ns * Low active power -- ICC = 90 mA @ 10 ns (Industrial) * Low CMOS standby power -- ISB2 = 10 mA * 2.0V data retention * Automatic power-down when deselected * TTL-compatible inputs and outputs * Easy memory expansion with CE and OE features * Available in Lead-Free 36-lead (400-mil) Molded SOJ V36 and 44-pin TSOP II ZS44 packages
Functional Description[1]
The CY7C1049DV33 is a high-performance CMOS Static RAM organized as 512K words by 8 bits. Easy memory expansion is provided by an active LOW Chip Enable (CE), an active LOW Output Enable (OE), and tri-state drivers. Writing to the device is accomplished by taking Chip Enable (CE) and Write Enable (WE) inputs LOW. Data on the eight I/O pins (I/O0 through I/O7) is then written into the location specified on the address pins (A0 through A18). Reading from the device is accomplished by taking Chip Enable (CE) and Output Enable (OE) LOW while forcing Write Enable (WE) HIGH. Under these conditions, the contents of the memory location specified by the address pins will appear on the I/O pins. The eight input/output pins (I/O0 through I/O7) are placed in a high-impedance state when the device is deselected (CE HIGH), the outputs are disabled (OE HIGH), or during a Write operation (CE LOW, and WE LOW). The CY7C1049DV33 is available in standard 400-mil-wide 36-pin SOJ package and 44-pin TSOP II package with center power and ground (revolutionary) pinout.
Logic Block Diagram
Pin Configuration
SO J Top View
A0 A1 A2 A3 A4 CE I/O0 I/O1 VCC GND I/O2 I/O3 WE A5 A6 A7 A8 A9 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 NC A18 A17 A16 A15 OE I/O7 I/O6 GND VCC I/O5 I/O4 A14 A13 A12 A11 A10 NC
TSOP II Top View NC NC A0 A1 A2 A3 A4 CE I/O0 I/O1 VCC VSS I/O2 I/O3 WE A5 A6 A7 A8 A9 NC NC
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23
I/O0
INPUT BUFFER
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10
I/O1
ROW DECODER SENSE AMPS
I/O2 I/O3 I/O4 I/O5
512K x 8
CE WE OE
COLUMN DECODER
POWER DOWN
I/O6 I/O7
Selection Guide
Maximum Access Time Maximum Operating Current Maximum CMOS Standby Current -10 (Industrial) 10 90 10 -12 (Automotive)[2] 12 95 15 Unit ns mA mA
Notes: 1. For guidelines on SRAM system design, please refer to the `System Design Guidelines' Cypress application note, available on the internet at www.cypress.com. 2. Automotive product information is Preliminary.
Cypress Semiconductor Corporation Document #: 38-05475 Rev. *C
A 11 A 12 A 13 A 14 A 15 A 16 A17 A18
NC NC NC A18 A17 A16 A15 OE I/O7 I/O6 VSS VCC I/O5 I/O4 A14 A13 A12 A11 A10 NC NC NC
*
198 Champion Court
*
San Jose, CA 95134-1709 * 408-943-2600 Revised April 3, 2006
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CY7C1049DV33
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature ................................. -65C to +150C Ambient Temperature with Power Applied............................................. -55C to +125C Supply Voltage on VCC to Relative GND[3] .... -0.3V to +4.6V DC Voltage Applied to Outputs in High-Z State[3] ....................................-0.3V to VCC + 0.3V DC Input Voltage[3] .................................-0.3V to VCC + 0.3V Current into Outputs (LOW)......................................... 20 mA Static Discharge Voltage............. ...............................>2001V (per MIL-STD-883, Method 3015) Latch-up Current...................................................... >200 mA
Operating Range
Range Industrial Automotive Ambient Temperature -40C to +85C -40C to +125C VCC 3.3V 0.3V 3.3V 0.3V Speed 10 ns 12 ns
Electrical Characteristics Over the Operating Range
-10 (Industrial) Parameter VOH VOL VIH[3] VIL[3] IIX IOZ ICC Description Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage[3] GND < VI < VCC GND < VOUT < VCC, Output Disabled VCC = Max., f = fMAX = 1/tRC 100MHz 83MHz 66MHz 40MHz ISB1 Automatic CE Power-down Current --TTL Inputs Automatic CE Power-down Current --CMOS Inputs Max. VCC, CE > VIH; VIN > VIH or VIN < VIL, f = fMAX Max. VCC, CE > VCC - 0.3V, VIN > VCC - 0.3V, or VIN < 0.3V, f = 0 Input Leakage Current Output Leakage Current VCC Operating Supply Current Test Conditions VCC = Min., IOH = -4.0 mA VCC = Min., IOL = 8.0 mA 2.0 -0.3 -1 -1 Min. 2.4 0.4 VCC + 0.3 0.8 +1 +1 90 80 70 60 20 2.0 -0.3 -1 -1 Max. -12 (Automotive) Min. 2.4 0.4 VCC + 0.3 0.8 +1 +1 95 85 75 25 Max. Unit V V V V A A mA mA mA mA mA
ISB2
10
15
mA
Capacitance[4]
Parameter CIN COUT Description Input Capacitance I/O Capacitance Test Conditions TA = 25C, f = 1 MHz, VCC = 3.3V Max. 8 8 Unit pF pF
Thermal Resistance[4]
Parameter JA JC Description Thermal Resistance (Junction to Ambient)[4] Thermal Resistance (Junction to Case)[4] Test Conditions Still Air, soldered on a 3 x 4.5 inch, two-layer printed circuit board SOJ Package 57.91 36.73 TSOP II Package 50.66 17.17 Unit C/W C/W
Notes: 3. VIL (min.) = -2.0V and VIH(max) = VCC + 2V for pulse durations of less than 20 ns. 4. Tested initially and after any design or process changes that may affect these parameters.
Document #: 38-05475 Rev. *C
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CY7C1049DV33
AC Test Loads and Waveforms[5]
10 ns device
OUTPUT 50 * CAPACITIVE LOAD CONSISTS OF ALL COMPONENTS OF THE TEST ENVIRONMENT High-Z characteristics: 3.3V OUTPUT 5 pF R2 351 1.5V Z = 50 3.0V 90% ALL INPUT PULSES 90% 10% 10%
30 pF*
GND
(a)
R 317
Rise Time: 1 V/ns
(b)
Fall Time: 1 V/ns
(c)
AC Switching
Parameter Read Cycle tpower[7] tRC tAA tOHA tACE tDOE tLZOE tHZOE tLZCE tHZCE tPU tPD tWC tSCE tAW tHA tSA tPWE tSD tHD tLZWE tHZWE
Characteristics[6]
Over the Operating Range -10 (Industrial) -12 (Automotive) Min. 100 12 10 3 10 5 0 5 3 5 0 10 10 7 7 0 0 7 5 0 3 5 12 8 8 0 0 8 6 0 3 6 0 12 3 6 0 6 3 12 6 12 Max. Unit s ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Description VCC(typical) to the first access Read Cycle Time Address to Data Valid Data Hold from Address Change CE LOW to Data Valid OE LOW to Data Valid OE LOW to Low-Z OE HIGH to CE LOW to High-Z[8, 9] Low-Z[9]
Min. 100 10
Max.
CE HIGH to High-Z[8, 9] CE LOW to Power-up CE HIGH to Power-down Write Cycle Time CE LOW to Write End Address Set-up to Write End Address Hold from Write End Address Set-up to Write Start WE Pulse Width Data Set-up to Write End Data Hold from Write End WE HIGH to Low-Z[9] WE LOW to High-Z[8, 9]
Write Cycle[10, 11]
Notes: 5. AC characteristics (except High-Z) are tested using the load conditions shown in Figure (a). High-Z characteristics are tested for all speeds using the test load shown in Figure (c). 6. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified IOL/IOH and 30-pF load capacitance. 7. tPOWER gives the minimum amount of time that the power supply should be at stable, typical VCC values until the first memory access can be performed. 8. tHZOE, tHZCE, and tHZWE are specified with a load capacitance of 5 pF as in part (d) of AC Test Loads. Transition is measured when the outputs enter a high impedance state. 9. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device. 10. The internal Write time of the memory is defined by the overlap of CE LOW, and WE LOW. CE and WE must be LOW to initiate a Write, and the transition of either of these signals can terminate the Write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the Write. 11. The minimum Write cycle time for Write Cycle No. 2 (WE controlled, OE LOW) is the sum of tHZWE and tSD.
Document #: 38-05475 Rev. *C
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CY7C1049DV33
Data Retention Characteristics Over the Operating Range
Parameter VDR ICCDR tCDR tR
[4]
Description VCC for Data Retention Data Retention Current Chip Deselect to Data Retention Time Operation Recovery Time
Conditions [13] VCC = VDR = 2.0V, CE > VCC - 0.3V VIN > VCC - 0.3V or VIN < 0.3V Ind'l Auto
Min. 2.0
Max 10 15
Unit V mA mA ns ns
0 tRC
[12]
Data Retention Waveform
DATA RETENTION MODE VCC 3.0V tCDR CE VDR > 2V 3.0V tR
Switching Waveforms
Read Cycle No. 1[14, 15]
tRC ADDRESS tAA tOHA DATA OUT PREVIOUS DATA VALID DATA VALID
Read Cycle No. 2 (OE Controlled)[15, 16]
ADDRESS tRC CE
tACE OE tDOE DATA OUT VCC SUPPLY CURRENT tLZOE HIGH IMPEDANCE tLZCE tPU 50% tHZOE tHZCE DATA VALID tPD 50% ISB ICC HIGH IMPEDANCE
Notes: 12. Full device operation requires linear VCC ramp from VDR to VCC(min.) > 50 s or stable at VCC(min.) > 50 s 13. No input may exceed VCC + 0.3V. 14. Device is continuously selected. OE, CE = VIL. 15. WE is HIGH for Read cycle. 16. Address valid prior to or coincident with CE transition LOW.
Document #: 38-05475 Rev. *C
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CY7C1049DV33
Switching Waveforms(continued)
Write Cycle No. 1 (WE Controlled, OE HIGH During Write)[17, 18]
tWC ADDRESS tSCE CE tAW tSA WE tPWE tHA
OE tSD DATA I/O NOTE 19 tHZOE DATAIN VALID tHD
Write Cycle No. 2 (WE Controlled, OE LOW)[18]
tWC ADDRESS tSCE CE
tAW tSA WE tSD DATA I/O NOTE 19 tHZWE
Notes: 17. Data I/O is high-impedance if OE = VIH. 18. If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high-impedance state. 19. During this period the I/Os are in the output state and input signals should not be applied.
tHA tPWE
tHD
DATA VALID tLZWE
Document #: 38-05475 Rev. *C
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CY7C1049DV33
Switching Waveforms(continued)
Write Cycle No. 3 (CE Controlled)[17, 18]
tWC ADDRESS tSCE CE tSA tSCE tAW tPWE WE tSD DATA I/O DATA VALID tHD tHA
Truth Table
CE H L L L OE X L X H WE X H L H I/O0-I/O7 High-Z Data Out Data In High-Z Power-down Read Write Selected, Outputs Disabled Mode Power Standby (ISB) Active (ICC) Active (ICC) Active (ICC)
Ordering Information
Speed (ns) 10 12 Ordering Code CY7C1049DV33-10VXI CY7C1049DV33-10ZSXI CY7C1049DV33-12VXE CY7C1049DV33-12ZSXE Package Name 51-85090 51-85087 51-85090 51-85087 Package Type 36-lead (400-Mil) Molded SOJ (Pb-Free) 44-pin TSOP II (Pb-Free) 36-lead (400-Mil) Molded SOJ (Pb-Free) 44-pin TSOP II (Pb-Free) Automotive Operating Range Industrial
Please contact your local Cypress sales representative for availability of these parts.
Document #: 38-05475 Rev. *C
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CY7C1049DV33
Package Diagrams
36-lead (400-mil) Molded SOJ (51-85090)
51-85090-*B
44-pin TSOP II (51-85087)
51-85087-*A
All product and company names mentioned in this document may be the trademarks of their respective holders. Document #: 38-05475 Rev. *C Page 7 of 8
(c) Cypress Semiconductor Corporation, 2006. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
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CY7C1049DV33
Document History Page
Document Title: CY7C1049DV33 4-Mbit (512K x 8) Static RAM Document Number: 38-05475 REV. ** *A *B ECN NO. 201560 233729 351096 Issue Date See ECN See ECN See ECN Orig. of Change SWI SYT PCI Description of Change Advance Data sheet for C9 IPP 1.AC, DC parameters are modified as per EROS(Spec # 01-2165) 2.Pb-free offering in the `ordering information' Changed from Advance to Preliminary Removed 20 ns Speed bin Corrected DC voltage (min) value in maximum ratings section from - 0.5 to - 0.3V Redefined ICC values for Com'l and Ind'l temperature ranges ICC (Com'l): Changed from 100, 80 and 67 mA to 90, 80 and 75 mA for 8, 10 and 12ns speed bins respectively ICC (Ind'l): Changed from 80 and 67 mA to 90 and 85 mA for 10 and 12ns speed bins respectively Added VIH(max) spec in Note# 2 Changed reference voltage level for measurement of Hi-Z parameters from 500 mV to 200 mV Added Data Retention Characteristics/Waveform and footnotes 11 and 12 Changed Package Diagram name from 44-pin TSOP II Z44 to 44-pin TSOP II ZS44 Changed part names from Z to ZS in the Ordering Information Table Added 8 ns parts in the Ordering Information Table Added Lead-Free Ordering Information Shaded Ordering Information Table Converted from Preliminary to Final Removed -8 speed bin Removed Commercial Operating Range product information Added Automotive Operating Range product information Updated Thermal Resistance table Updated footnote #8 on High-Z parameter measurement Replaced Package Name column with Package Diagram in the Ordering Information table
*C
446328
See ECN
NXR
Document #: 38-05475 Rev. *C
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